Memory can generally be characterized as either volatile or non-volatile. Volatile memory, for example, most types of random access memory (RAM), requires constant power to maintain stored information. Non-volatile memory does not require power to maintain stored information. Various types of non-volatile memories include read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs).
Flash memory is a type of EEPROM that is programmed and erased in blocks as opposed to cells. A conventional flash memory device includes a plurality of memory cells, each cell is provided with a floating gate covered with an insulating layer. There is also a control gate which overlays the insulating layer. Below the floating gate is another insulating layer sandwiched between the floating gate and the cell substrate. This insulating layer is an oxide layer and is often referred to as the tunnel oxide. The substrate contains doped source and drain regions, with a channel region disposed between the source and drain regions. In a flash memory device, a charged floating gate represents one logic state, e.g., a logic value “0”, while a non-charged floating gate represents the opposite logic state e.g., a logic value “1”. The flash memory cell is programmed by placing the floating gate into one of these charged states. Charges may be injected or written on to the floating gate by any number of methods, including e.g., avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron (CHE) injection. The floating gate may be discharged or erased by any number of methods including e.g., Fowler-Nordheim tunneling. This type of flash memory element is a transistor-based non-volatile memory element.
The “NAND” and “NOR” architectures are two common types of flash memory architectures. NAND flash memory has gained widespread popularity over NOR flash memory because it can pack a greater number of storage cells in a given area of silicon, providing NAND with density and cost advantages over other nonvolatile memory. A NAND flash memory device typically utilizes a NAND flash controller to write data to the NAND in a page-by-page fashion. An example NAND memory array 10 is illustrated in FIG. 1. Pages 12 are typically grouped into blocks 14, where a block is the smallest erasable unit of the NAND flash memory device. For example, and without limitation, a typical NAND flash memory device contains 2,112 bytes of memory per page 12 and 64 or 128 pages of memory are contained in a block 14. FIG. 1 illustrates blocks 14 comprising 64 pages 12. For a page 12 having 2,112 bytes in total, there is a 2,048-byte data area 16 and a 64-byte spare area 18. The spare area 18 is typically used for error correction code (ECC), redundancy cells, and/or other software overhead functions. The smallest entity that can be programmed in the illustrated array 10 is a bit.
FIG. 2 illustrates a NAND flash memory device 110 having a memory array 120 and sense circuitry 130 connected to the memory array 120 by data lines, which are commonly referred to as bitlines (BL). The array 120 comprises typical transistor-based non-volatile flash memory elements. When data is to be written into the NAND memory array, the data is initially loaded into the sense circuitry 130. Once the data is latched, a programming operation is used to write a page of data into one of the pages of memory cells in the memory array 120. The sense circuitry 130 typically comprises volatile static or dynamic memory elements.
A simplified schematic of a portion of the sense circuitry 130 is illustrated in FIG. 3. As can be seen, there is sense operation circuitry 132 comprising three n-channel MOSFET transistors 134, 136, 138, a data latch 140, cache latch 150 and additional n-channel MOSFET transistors 160, 162, 164, 166, 168. The data latch 140 is illustrated as comprising cross-coupled inverters 142, 144. The cache latch 150 is illustrated as comprising cross-coupled inverters 152, 154. The inverters 142, 144, 152, 154 may each consist of e.g., an n-channel CMOS transistor and a p-channel CMOS transistor configured such that their gates are coupled together and at least one source/drain node of the n-channel transistor is coupled to a source/drain node of the p-channel transistor. Thus, the data and cache latches 140, 150 in the illustrated example are implemented as static memory elements, which would lose their contents if power were removed from the circuit 130. Thus, a situation could arise where latched data could be lost if power to the array 110 (FIG. 2) were lost before the latched data was copied into the NAND memory arrays. Accordingly, the inventor of the present application appreciated that it would be desirable to prevent latched information from being lost in the event of a power failure or similar condition.
Continuing with the FIG. 3 example, data Da, Db is input into the sense circuitry 130 through the cache latch 150 when a data load/output enable signal data_load/out_en, connected to the gates of transistors 166, 168, is activated. Typically, data Da is the complement of data Db, and vice versa. A data signal Data connected at the gate of transistor 160 couples the data latch 140 to the cache latch 150. When the data signal Data is at a level that activates transistor 160, latched data is transferred from the cache latch 150 to the data latch 140. A verify enable signal, verify_en, is used to activate transistor 162, which is connected to transistor 164. The gate of transistor 164 is connected to the data latch 140. The same node of transistor 160 that is connected to the data latch 140 is also connected to a node of transistor 138 within the sense operation circuitry 132. A precharge enable signal, precharge_en, controls transistor 136 while a bitline sensing signal, blsn, controls transistor 134. A node of transistor 134 is connected to a write multiplexer (wmux) where data-to-be written, dw, based on the input data, is sent to and eventually stored in a conventional non-volatile memory array, which utilizes transistor-based memory elements.
As can be seen from the illustrated example, many transistors are required to implement the sense circuitry 130. It is desirable to reduce the circuitry used in sense circuitry 130. It is also desirable to increase the speed of sense circuitry 130.